try the follow pll model and replace its paras as 4046, good luck!
* fichier pll.cir
.lib eval.lib ; contient logique et analogique
.model Rvar VSWITCH (Ron=450 Roff=850 Voff=1.8 Von=1)
.subckt vco in fout
S1 10 11 in 0 Rvar
X1 10 11 7414 PARAMS: IO_LEVEL=3
X2 11 12 7404
C1 10 12 5n
X3 15 13 12 14 fout 13 7474
VDD 14 0 DC 5
Rclear 14 15 100
Cclear 15 0 10n
.ends
X3 1 2 3 7486
R3 3 4 16.8k
C2 4 5 10n
Rs 5 0 1.8k
X1 4 2 vco
Rfs1 4 7 180k
Cfs 7 0 0.1n
Vcom 6 0 pulse (1.15 1.35 199u 2u 2u 198u 400u)
*Vcom 6 0 sin (1.25 .1 2k 0 0 0)
X2 6 1 vco
.IC V(X1.15)=0
.IC V(X2.15)=0
.IC V(4)=1.1
.IC V(7)=1.1
.probe
.tran 1u 800u
.end
[此贴子已经被作者于2004-7-19 13:59:05编辑过] |